Fast Charge Pump Circuit for PLL using 50nm CMOS Technology

PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The performance of charge pumps depends heavily on the ability to efficiently generate high voltages on-chip while meeting stringent power and area requirements. The paper presents a High Speed CMOS charge pump circuit for PLL applications using 50nm CMOS technology that operates at 1V. The proposed circuit has simple symmetric structure and provides more stable operation while reducing spurious jump phenomenon. The output voltage of presented design can be increased up to 1015mV. The functionality of charge pump has been tested at operating based frequency of 400 MHz.